Let's make a Pi Pico 2 powered video card.
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Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.
I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.
What does that all mean? We have smiley faces!
Now I get to translate this hot mess into Verilog.
Yay.
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Now I get to translate this hot mess into Verilog.
Yay.
the nice thing is i can just export things to GPIO pins, and then just look at the signal in the simulation and on my scope, and just visually check that they're doing the same thing
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Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.
I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.
What does that all mean? We have smiley faces!
@gloriouscow I realized I only understand about 1/8 of all the things you say here. But I'm 100% here for this content.
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@gloriouscow I realized I only understand about 1/8 of all the things you say here. But I'm 100% here for this content.
@970uts1d3 that's fine, I understand less than 1/8 of what i post
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@970uts1d3 that's fine, I understand less than 1/8 of what i post
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@970uts1d3 that's fine, I understand less than 1/8 of what i post
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the nice thing is i can just export things to GPIO pins, and then just look at the signal in the simulation and on my scope, and just visually check that they're doing the same thing
Good enough, ship it
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Good enough, ship it
I made it worse
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I made it worse
@gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.
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I made it worse
The final version should probably not do this
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@gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.
@ChuckMcManis digital can export your simulation to Verilog but it's quite ugly. I'm wanting to make something you can actually read that isn't just thirty chips tied together
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I made it worse
@gloriouscow sometimes my headspace looks like this
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@gloriouscow sometimes my headspace looks like this
@lucybarky col-arf-ul?
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I made it worse
@gloriouscow That is gorgeous. I’d totally make a floor mat with that pattern. -
@lucybarky col-arf-ul?
@gloriouscow precisely.
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The final version should probably not do this
I found a pretty decent way of checking my work against the digital simulation.
We can just run the card in a test harness in iVerilog, and export a CSV of signal states, so we can do a direct comparison against a CSV dumped from Digital.
This is a whole lot easier than using the oscilloscope lol.
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I found a pretty decent way of checking my work against the digital simulation.
We can just run the card in a test harness in iVerilog, and export a CSV of signal states, so we can do a direct comparison against a CSV dumped from Digital.
This is a whole lot easier than using the oscilloscope lol.
Then you find yourself in the frustrating situation where all your signals match but your video card still emits tutti frutti.
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Then you find yourself in the frustrating situation where all your signals match but your video card still emits tutti frutti.
solution: MOAR SIGNALS
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solution: MOAR SIGNALS
It helps not to wire your DRAM address pins backwards.
Still major issues to iron out.
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It helps not to wire your DRAM address pins backwards.
Still major issues to iron out.
@gloriouscow i love this sentence.
