Let's make a Pi Pico 2 powered video card.
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@gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.
@ChuckMcManis digital can export your simulation to Verilog but it's quite ugly. I'm wanting to make something you can actually read that isn't just thirty chips tied together
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I made it worse
@gloriouscow sometimes my headspace looks like this
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@gloriouscow sometimes my headspace looks like this
@lucybarky col-arf-ul?
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I made it worse
@gloriouscow That is gorgeous. I’d totally make a floor mat with that pattern. -
@lucybarky col-arf-ul?
@gloriouscow precisely.
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The final version should probably not do this
I found a pretty decent way of checking my work against the digital simulation.
We can just run the card in a test harness in iVerilog, and export a CSV of signal states, so we can do a direct comparison against a CSV dumped from Digital.
This is a whole lot easier than using the oscilloscope lol.
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I found a pretty decent way of checking my work against the digital simulation.
We can just run the card in a test harness in iVerilog, and export a CSV of signal states, so we can do a direct comparison against a CSV dumped from Digital.
This is a whole lot easier than using the oscilloscope lol.
Then you find yourself in the frustrating situation where all your signals match but your video card still emits tutti frutti.
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Then you find yourself in the frustrating situation where all your signals match but your video card still emits tutti frutti.
solution: MOAR SIGNALS
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solution: MOAR SIGNALS
It helps not to wire your DRAM address pins backwards.
Still major issues to iron out.
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It helps not to wire your DRAM address pins backwards.
Still major issues to iron out.
@gloriouscow i love this sentence.
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It helps not to wire your DRAM address pins backwards.
Still major issues to iron out.
We're getting there. Still have an issue with alignment of glyphs and attributes.
I'm not sure how, since my latch signals for characters and attributes match the simulation. But baffling bugs are the best kind of bugs.
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We're getting there. Still have an issue with alignment of glyphs and attributes.
I'm not sure how, since my latch signals for characters and attributes match the simulation. But baffling bugs are the best kind of bugs.
its still kind of weird seeing like, readable text on a monitor, and knowing this isn't IBM or Tseng Labs or Cirrus Logic it's just GloriousCow.
I made a video card?? you can just do that? isn't it illegal?
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its still kind of weird seeing like, readable text on a monitor, and knowing this isn't IBM or Tseng Labs or Cirrus Logic it's just GloriousCow.
I made a video card?? you can just do that? isn't it illegal?
There's a lot of ways I could just change the way the card works that would probably be absolutely fine and would be less of a pain in the ass to implement and debug, but there's something pleasing about matching the schematics.
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I made it worse
@gloriouscow this is a fundamental experience of outputting video out of an FPGA lol
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R relay@relay.infosec.exchange shared this topic
