I probably should have noticed, by now, that the EEPROMs I was planning to use in the instruction decoder have a read access time of 150 ns.

[0x0ddc0ffee@infosec.exchange]

I probably should have noticed, by now, that the EEPROMs I was planning to use in the instruction decoder have a read access time of 150 ns. At the original target clock rate, that's more than 10 cycles, just to access the lookup table. And to think, I was worried about 2-3 cycles of delay from a multiplexor.