i just realized id love to have a signed 1 bit type actually.

[sudo200@layer8.space]

@mothcompute @chfour

I mean, it is literally designed to be as absolutely minimal and simple as possible, but still

[mothcompute@merping.synth.download]

@sudo200 honestly i learned everything i know about amd microcode out of two pdfs and five markdown files; im not sure its that far out of reach if youre interested in learning it

[lilahexe@fedi.lilahexe.top]

@domi @mothcompute this reminds me of the boolean with three states I saw in a production codebase: true, false and undefined

[mothcompute@merping.synth.download]

@LilaHexe @domi ive seen stuff like that before and i always wonder if theyve just never heard of ternary logic or something

[domi@donotsta.re]

@mothcompute@merping.synth.download @chfour@merping.synth.download this reminds me. my main pc is a 3700X now. and i have a spare 3600 after an upgrade

... you know. maybe i really should look into it. I wonder how much shenanigans could I get away with

[sudo200@layer8.space]

@mothcompute

That sounds a lot simpler than I expected. Yes, I would be interested in redefining what my CPU does

[mothcompute@merping.synth.download]

@domi @chfour if nothing else its worth it for access to the architectural 'machine segment,' which seems to have unprotected read-write access to not just msrs but also like. cache and various internal state variables and microcode and stuff maybe?

[domi@donotsta.re]

@mothcompute@merping.synth.download @chfour@merping.synth.download you know. i really want to run windows 95 inside the cache. there's enough of it

[jn@boopsnoot.de]

@domi @mothcompute @chfour coreboot weekend project /j

[mothcompute@merping.synth.download]

@domi @chfour i do assume that would be harder just since windows likely assumes (otherwise rightly so) that any page it flushes will be valid targets for an isa or pci dma operation, and so probably doesnt tag such pages explicitly in a way that a cache only system could differentiate automatically

[mothcompute@merping.synth.download]

@domi @chfour i have no idea about this though ive never looked into it

[mothcompute@merping.synth.download]

@domi @chfour though if you were to do it under svm and simply trap any device accesses that might work...

[noisytoot@berkeley.edu.pl]

@domi @mothcompute @chfour unfortunately I don't think modern AMD supports cache-as-RAM (PSP does raminit instead)