i just realized id love to have a signed 1 bit type actually.

[chfour@merping.synth.download]

@mothcompute thats cool

[sudo200@layer8.space]

@mothcompute

Yeah, just casually writing your own microcode.

I feel inadequate to be around you now tbh.

[mothcompute@merping.synth.download]

@sudo200 @chfour generally speaking i believe in cisc design principles, so without a doubt variable length, lots of orthogonality, and a lot of compound instructions. but unlike x86 the instruction stream would be self synchronizing, which makes it much easier to decode instructions and fetch and sequence microoperations ahead of execution

[sudo200@layer8.space]

@mothcompute @chfour

Interesting. I have a MISC ISA spec (if you can call it that) laying about somewhere, which is basically the exact opposite

[mothcompute@merping.synth.download]

@sudo200 @chfour cpus have done predecode for decades now but i think with higher level source machine code and self synchronization that lets you get away with much more intelligent and of course much more parallel reordering, and in ideal cases the ability to do the entire decode step for an instruction page ahead of execution, whereupon you can simply copy them verbatim into the pipeline without actually decoding anything in realtime. the catch is it uses a whole lot of power and die space

[mothcompute@merping.synth.download]

@sudo200 @chfour i think in many respects cisc machine code is simply ir, so the more symbolic and less literal it is the better chance you get at runtime to optimize it for the underlying silicon, which is really all compilers do

[sudo200@layer8.space]

@mothcompute @chfour

I mean, it is literally designed to be as absolutely minimal and simple as possible, but still

[mothcompute@merping.synth.download]

@sudo200 honestly i learned everything i know about amd microcode out of two pdfs and five markdown files; im not sure its that far out of reach if youre interested in learning it

[lilahexe@fedi.lilahexe.top]

@domi @mothcompute this reminds me of the boolean with three states I saw in a production codebase: true, false and undefined

[mothcompute@merping.synth.download]

@LilaHexe @domi ive seen stuff like that before and i always wonder if theyve just never heard of ternary logic or something

[domi@donotsta.re]

@mothcompute@merping.synth.download @chfour@merping.synth.download this reminds me. my main pc is a 3700X now. and i have a spare 3600 after an upgrade

... you know. maybe i really should look into it. I wonder how much shenanigans could I get away with

[sudo200@layer8.space]

@mothcompute

That sounds a lot simpler than I expected. Yes, I would be interested in redefining what my CPU does

[mothcompute@merping.synth.download]

@domi @chfour if nothing else its worth it for access to the architectural 'machine segment,' which seems to have unprotected read-write access to not just msrs but also like. cache and various internal state variables and microcode and stuff maybe?

[domi@donotsta.re]

@mothcompute@merping.synth.download @chfour@merping.synth.download you know. i really want to run windows 95 inside the cache. there's enough of it

[jn@boopsnoot.de]

@domi @mothcompute @chfour coreboot weekend project /j

[mothcompute@merping.synth.download]

@domi @chfour i do assume that would be harder just since windows likely assumes (otherwise rightly so) that any page it flushes will be valid targets for an isa or pci dma operation, and so probably doesnt tag such pages explicitly in a way that a cache only system could differentiate automatically

[mothcompute@merping.synth.download]

@domi @chfour i have no idea about this though ive never looked into it

[mothcompute@merping.synth.download]

@domi @chfour though if you were to do it under svm and simply trap any device accesses that might work...

[noisytoot@berkeley.edu.pl]

@domi @mothcompute @chfour unfortunately I don't think modern AMD supports cache-as-RAM (PSP does raminit instead)