i just realized id love to have a signed 1 bit type actually.
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honestly i might try implementing this on zen 2 if i can find an appropriate instruction to override
@mothcompute like in microcode?
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@mothcompute like in microcode?
@chfour yes itll be awesome
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@chfour yes itll be awesome
I would really like to know how your ideal ISA would look like.
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@chfour yes itll be awesome
@mothcompute thats cool
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honestly i might try implementing this on zen 2 if i can find an appropriate instruction to override
Yeah, just casually writing your own microcode.
I feel inadequate to be around you now tbh.
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I would really like to know how your ideal ISA would look like.
@sudo200 @chfour generally speaking i believe in cisc design principles, so without a doubt variable length, lots of orthogonality, and a lot of compound instructions. but unlike x86 the instruction stream would be self synchronizing, which makes it much easier to decode instructions and fetch and sequence microoperations ahead of execution
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@sudo200 @chfour generally speaking i believe in cisc design principles, so without a doubt variable length, lots of orthogonality, and a lot of compound instructions. but unlike x86 the instruction stream would be self synchronizing, which makes it much easier to decode instructions and fetch and sequence microoperations ahead of execution
Interesting. I have a MISC ISA spec (if you can call it that) laying about somewhere, which is basically the exact opposite
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@sudo200 @chfour generally speaking i believe in cisc design principles, so without a doubt variable length, lots of orthogonality, and a lot of compound instructions. but unlike x86 the instruction stream would be self synchronizing, which makes it much easier to decode instructions and fetch and sequence microoperations ahead of execution
@sudo200 @chfour cpus have done predecode for decades now but i think with higher level source machine code and self synchronization that lets you get away with much more intelligent and of course much more parallel reordering, and in ideal cases the ability to do the entire decode step for an instruction page ahead of execution, whereupon you can simply copy them verbatim into the pipeline without actually decoding anything in realtime. the catch is it uses a whole lot of power and die space
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@sudo200 @chfour cpus have done predecode for decades now but i think with higher level source machine code and self synchronization that lets you get away with much more intelligent and of course much more parallel reordering, and in ideal cases the ability to do the entire decode step for an instruction page ahead of execution, whereupon you can simply copy them verbatim into the pipeline without actually decoding anything in realtime. the catch is it uses a whole lot of power and die space
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Interesting. I have a MISC ISA spec (if you can call it that) laying about somewhere, which is basically the exact opposite
I mean, it is literally designed to be as absolutely minimal and simple as possible, but still
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Yeah, just casually writing your own microcode.
I feel inadequate to be around you now tbh.
@sudo200 honestly i learned everything i know about amd microcode out of two pdfs and five markdown files; im not sure its that far out of reach if youre interested in learning it
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@mothcompute@merping.synth.download the logical conclusion of IEE754 is 2-bit "float": representing -1, 1, 0 or NaN
@domi @mothcompute this reminds me of the boolean with three states I saw in a production codebase: true, false and undefined
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@domi @mothcompute this reminds me of the boolean with three states I saw in a production codebase: true, false and undefined
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@chfour yes itll be awesome
@mothcompute@merping.synth.download @chfour@merping.synth.download this reminds me. my main pc is a 3700X now. and i have a spare 3600 after an upgrade
... you know. maybe i really should look into it. I wonder how much shenanigans could I get away with
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@sudo200 honestly i learned everything i know about amd microcode out of two pdfs and five markdown files; im not sure its that far out of reach if youre interested in learning it
That sounds a lot simpler than I expected. Yes, I would be interested in redefining what my CPU does
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@mothcompute@merping.synth.download @chfour@merping.synth.download this reminds me. my main pc is a 3700X now. and i have a spare 3600 after an upgrade
... you know. maybe i really should look into it. I wonder how much shenanigans could I get away with
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@mothcompute@merping.synth.download @chfour@merping.synth.download you know. i really want to run windows 95 inside the cache. there's enough of it
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@mothcompute@merping.synth.download @chfour@merping.synth.download you know. i really want to run windows 95 inside the cache. there's enough of it
@domi @mothcompute @chfour coreboot weekend project /j
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@mothcompute@merping.synth.download @chfour@merping.synth.download you know. i really want to run windows 95 inside the cache. there's enough of it
@domi @chfour i do assume that would be harder just since windows likely assumes (otherwise rightly so) that any page it flushes will be valid targets for an isa or pci dma operation, and so probably doesnt tag such pages explicitly in a way that a cache only system could differentiate automatically
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@domi @chfour i do assume that would be harder just since windows likely assumes (otherwise rightly so) that any page it flushes will be valid targets for an isa or pci dma operation, and so probably doesnt tag such pages explicitly in a way that a cache only system could differentiate automatically
