Let's make a Pi Pico 2 powered video card.
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@ldcd correct there's no clock line on the video connector. The monitor has PLLs to synchronize to vertical and horizontal frequencies within a certain range. A CGA monitor expects a 15.7kHZ hsync, for example. The signal, although digital in color, is put through analog circuit and so the monitor does not have to sample colors.
The Pi in the rgb2hdmi is sampling the color at a certain period within a dot window. If I am writing colors out of phase with the sampling then we will have various flickering going on. Why only in those specific areas? I am not really sure.
@gloriouscow hmm I wonder if you're seeing some crosstalk between the different lines? Breadboards tend to have a lot of parasitics
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@gloriouscow hmm I wonder if you're seeing some crosstalk between the different lines? Breadboards tend to have a lot of parasitics
@gloriouscow hmm actually I don't think that would do it
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@gloriouscow hmm actually I don't think that would do it
@gloriouscow dumb question but have you checked HSYNC and VSYNC with a scope? I've had some monitors (although HDMI so probably quite different) where I've inverted or neglected one or the other and the PLL still sorta locks and you get an image
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I do have a de10 nano FPGA board. It's in my MiSTer. Which I never use!
@gloriouscow A bit more expensive than 2 x $5 though
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@gloriouscow A bit more expensive than 2 x $5 though
I don't think you need anything near that to make a CGA, but yeah, anything with an FPGA is going to be a bit more expensive.
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I do have a de10 nano FPGA board. It's in my MiSTer. Which I never use!
Right. This isn't completely baffling or anything
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Right. This isn't completely baffling or anything
Oh, wait, I remember this level from ZZT.
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Oh, wait, I remember this level from ZZT.
I think the elf needs food badly
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I think the elf needs food badly
okay this isn't that confusing
for example, these are the snake pins. you can choose from left snakes or right snakes
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Right. This isn't completely baffling or anything
@gloriouscow this seems like something @paulrickards would generate and send to his plotter
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I'm starting to think a pico is not the appropriate thing to build a video card with.
all my fun ideas always end up with me concluding i should use an FPGA.
FPGAs are like the crabs of electronics projects. everything wants to turn into an FPGA if you give it enough time.
@gloriouscow are DSPs horribly unfashionable now? I remember for a minute in the 90s, everything was a DSP
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@gloriouscow this seems like something @paulrickards would generate and send to his plotter
@robdaemon @gloriouscow Totally, I'd plot that
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okay this isn't that confusing
for example, these are the snake pins. you can choose from left snakes or right snakes
you know, there's a very good reason NOT to use an FPGA
when you actually use the proper tools for a job, it stops becoming a hack.
you're no longer a hacker, you're some kind of engineer or something. ugh.
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you know, there's a very good reason NOT to use an FPGA
when you actually use the proper tools for a job, it stops becoming a hack.
you're no longer a hacker, you're some kind of engineer or something. ugh.
Well, I did an FPGA thing. Can check that off the bucket list.
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okay this isn't that confusing
for example, these are the snake pins. you can choose from left snakes or right snakes
@gloriouscow this pin only does rising edges
That pin only does falling edges
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Well, I did an FPGA thing. Can check that off the bucket list.
“That's why they call me the Count!” —you, probably
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“That's why they call me the Count!” —you, probably
@argv_minus_one nobody has ever called me the count, and i hope they do not start
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Well, I did an FPGA thing. Can check that off the bucket list.
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Well, I did an FPGA thing. Can check that off the bucket list.
Okay, lets see if I can get a 14.31818MHz clock out of this thing.
We have a 50MHz clock source, on a pin called FPGA_CLK1_50.
How do we get 14.31818MHz out of that?
By attaching a PLL to it, hopefully.
module de10_clock_test (
input wire FPGA_CLK1_50,
output wire GPIO_1_0
);
wire clk_osc;
wire pll_locked;
cga_pll pll_inst (
.refclk (FPGA_CLK1_50),
.rst (1'b0),
.outclk_0 (clk_osc),
.locked (pll_locked)
);
assign GPIO_1_0 = clk_osc;
endmodule -
Okay, lets see if I can get a 14.31818MHz clock out of this thing.
We have a 50MHz clock source, on a pin called FPGA_CLK1_50.
How do we get 14.31818MHz out of that?
By attaching a PLL to it, hopefully.
module de10_clock_test (
input wire FPGA_CLK1_50,
output wire GPIO_1_0
);
wire clk_osc;
wire pll_locked;
cga_pll pll_inst (
.refclk (FPGA_CLK1_50),
.rst (1'b0),
.outclk_0 (clk_osc),
.locked (pll_locked)
);
assign GPIO_1_0 = clk_osc;
endmodulepll_instis a PLL instantiation. But notice it says nothing about like dividers or anything. We have to go into something confusingly called the IP (Incendiary Pickle) Catalog to actually configure the PLL.This is far as a I get because doing this causes Quartus to hang.
