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CIRCLE WITH A DOT

  1. Home
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  3. Let's make a Pi Pico 2 powered video card.

Let's make a Pi Pico 2 powered video card.

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retrocomputing
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  • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

    Turns out the 244 buffer I pulled out of my cheapo amazon special Box o' Components was just bad, or maybe I inadvertently killed it.

    In any case, I replaced it with one from the Chameleon and most of my signal issues cleared right up.

    gloriouscow@oldbytes.spaceG This user is from outside of this forum
    gloriouscow@oldbytes.spaceG This user is from outside of this forum
    gloriouscow@oldbytes.space
    wrote last edited by
    #120

    Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.

    I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.

    What does that all mean? We have smiley faces!

    Link Preview Image
    gloriouscow@oldbytes.spaceG 970uts1d3@defcon.social9 2 Replies Last reply
    0
    • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

      Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.

      I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.

      What does that all mean? We have smiley faces!

      Link Preview Image
      gloriouscow@oldbytes.spaceG This user is from outside of this forum
      gloriouscow@oldbytes.spaceG This user is from outside of this forum
      gloriouscow@oldbytes.space
      wrote last edited by
      #121

      Now I get to translate this hot mess into Verilog.

      Yay.

      Link Preview Image
      gloriouscow@oldbytes.spaceG 1 Reply Last reply
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      • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

        Now I get to translate this hot mess into Verilog.

        Yay.

        Link Preview Image
        gloriouscow@oldbytes.spaceG This user is from outside of this forum
        gloriouscow@oldbytes.spaceG This user is from outside of this forum
        gloriouscow@oldbytes.space
        wrote last edited by
        #122

        the nice thing is i can just export things to GPIO pins, and then just look at the signal in the simulation and on my scope, and just visually check that they're doing the same thing

        gloriouscow@oldbytes.spaceG 1 Reply Last reply
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        • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

          Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.

          I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.

          What does that all mean? We have smiley faces!

          Link Preview Image
          970uts1d3@defcon.social9 This user is from outside of this forum
          970uts1d3@defcon.social9 This user is from outside of this forum
          970uts1d3@defcon.social
          wrote last edited by
          #123

          @gloriouscow I realized I only understand about 1/8 of all the things you say here. But I'm 100% here for this content.

          gloriouscow@oldbytes.spaceG 1 Reply Last reply
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          • 970uts1d3@defcon.social9 970uts1d3@defcon.social

            @gloriouscow I realized I only understand about 1/8 of all the things you say here. But I'm 100% here for this content.

            gloriouscow@oldbytes.spaceG This user is from outside of this forum
            gloriouscow@oldbytes.spaceG This user is from outside of this forum
            gloriouscow@oldbytes.space
            wrote last edited by
            #124

            @970uts1d3 that's fine, I understand less than 1/8 of what i post

            970uts1d3@defcon.social9 2 Replies Last reply
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            • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

              @970uts1d3 that's fine, I understand less than 1/8 of what i post

              970uts1d3@defcon.social9 This user is from outside of this forum
              970uts1d3@defcon.social9 This user is from outside of this forum
              970uts1d3@defcon.social
              wrote last edited by
              #125

              @gloriouscow 😆

              1 Reply Last reply
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              • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                @970uts1d3 that's fine, I understand less than 1/8 of what i post

                970uts1d3@defcon.social9 This user is from outside of this forum
                970uts1d3@defcon.social9 This user is from outside of this forum
                970uts1d3@defcon.social
                wrote last edited by
                #126

                @gloriouscow 😆

                1 Reply Last reply
                0
                • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                  the nice thing is i can just export things to GPIO pins, and then just look at the signal in the simulation and on my scope, and just visually check that they're doing the same thing

                  gloriouscow@oldbytes.spaceG This user is from outside of this forum
                  gloriouscow@oldbytes.spaceG This user is from outside of this forum
                  gloriouscow@oldbytes.space
                  wrote last edited by
                  #127

                  Good enough, ship it

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                  gloriouscow@oldbytes.spaceG 1 Reply Last reply
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                  • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                    Good enough, ship it

                    Link Preview Image
                    gloriouscow@oldbytes.spaceG This user is from outside of this forum
                    gloriouscow@oldbytes.spaceG This user is from outside of this forum
                    gloriouscow@oldbytes.space
                    wrote last edited by
                    #128

                    I made it worse

                    Link Preview Image
                    chuckmcmanis@chaos.socialC gloriouscow@oldbytes.spaceG lucybarky@floofy.techL jodhus@deep13.socialJ goopadrew@infosec.exchangeG 5 Replies Last reply
                    0
                    • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                      I made it worse

                      Link Preview Image
                      chuckmcmanis@chaos.socialC This user is from outside of this forum
                      chuckmcmanis@chaos.socialC This user is from outside of this forum
                      chuckmcmanis@chaos.social
                      wrote last edited by
                      #129

                      @gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.

                      gloriouscow@oldbytes.spaceG 1 Reply Last reply
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                      • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                        I made it worse

                        Link Preview Image
                        gloriouscow@oldbytes.spaceG This user is from outside of this forum
                        gloriouscow@oldbytes.spaceG This user is from outside of this forum
                        gloriouscow@oldbytes.space
                        wrote last edited by
                        #130

                        The final version should probably not do this

                        gloriouscow@oldbytes.spaceG 1 Reply Last reply
                        0
                        • chuckmcmanis@chaos.socialC chuckmcmanis@chaos.social

                          @gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.

                          gloriouscow@oldbytes.spaceG This user is from outside of this forum
                          gloriouscow@oldbytes.spaceG This user is from outside of this forum
                          gloriouscow@oldbytes.space
                          wrote last edited by
                          #131

                          @ChuckMcManis digital can export your simulation to Verilog but it's quite ugly. I'm wanting to make something you can actually read that isn't just thirty chips tied together

                          1 Reply Last reply
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                          • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                            I made it worse

                            Link Preview Image
                            lucybarky@floofy.techL This user is from outside of this forum
                            lucybarky@floofy.techL This user is from outside of this forum
                            lucybarky@floofy.tech
                            wrote last edited by
                            #132

                            @gloriouscow sometimes my headspace looks like this

                            gloriouscow@oldbytes.spaceG 1 Reply Last reply
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                            • lucybarky@floofy.techL lucybarky@floofy.tech

                              @gloriouscow sometimes my headspace looks like this

                              gloriouscow@oldbytes.spaceG This user is from outside of this forum
                              gloriouscow@oldbytes.spaceG This user is from outside of this forum
                              gloriouscow@oldbytes.space
                              wrote last edited by
                              #133

                              @lucybarky col-arf-ul?

                              lucybarky@floofy.techL 1 Reply Last reply
                              0
                              • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                                I made it worse

                                Link Preview Image
                                jodhus@deep13.socialJ This user is from outside of this forum
                                jodhus@deep13.socialJ This user is from outside of this forum
                                jodhus@deep13.social
                                wrote last edited by
                                #134
                                @gloriouscow That is gorgeous. I’d totally make a floor mat with that pattern.
                                1 Reply Last reply
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                                • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                                  @lucybarky col-arf-ul?

                                  lucybarky@floofy.techL This user is from outside of this forum
                                  lucybarky@floofy.techL This user is from outside of this forum
                                  lucybarky@floofy.tech
                                  wrote last edited by
                                  #135

                                  @gloriouscow precisely.

                                  1 Reply Last reply
                                  0
                                  • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                                    The final version should probably not do this

                                    gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                    gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                    gloriouscow@oldbytes.space
                                    wrote last edited by
                                    #136

                                    I found a pretty decent way of checking my work against the digital simulation.

                                    We can just run the card in a test harness in iVerilog, and export a CSV of signal states, so we can do a direct comparison against a CSV dumped from Digital.

                                    This is a whole lot easier than using the oscilloscope lol.

                                    Link Preview Image
                                    gloriouscow@oldbytes.spaceG 1 Reply Last reply
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                                    • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                                      I found a pretty decent way of checking my work against the digital simulation.

                                      We can just run the card in a test harness in iVerilog, and export a CSV of signal states, so we can do a direct comparison against a CSV dumped from Digital.

                                      This is a whole lot easier than using the oscilloscope lol.

                                      Link Preview Image
                                      gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                      gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                      gloriouscow@oldbytes.space
                                      wrote last edited by
                                      #137

                                      Then you find yourself in the frustrating situation where all your signals match but your video card still emits tutti frutti.

                                      gloriouscow@oldbytes.spaceG 1 Reply Last reply
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                                      • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                                        Then you find yourself in the frustrating situation where all your signals match but your video card still emits tutti frutti.

                                        gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                        gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                        gloriouscow@oldbytes.space
                                        wrote last edited by
                                        #138

                                        solution: MOAR SIGNALS

                                        gloriouscow@oldbytes.spaceG 1 Reply Last reply
                                        0
                                        • gloriouscow@oldbytes.spaceG gloriouscow@oldbytes.space

                                          solution: MOAR SIGNALS

                                          gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                          gloriouscow@oldbytes.spaceG This user is from outside of this forum
                                          gloriouscow@oldbytes.space
                                          wrote last edited by
                                          #139

                                          It helps not to wire your DRAM address pins backwards.

                                          Still major issues to iron out.

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                                          mavu@mastodon.socialM gloriouscow@oldbytes.spaceG 2 Replies Last reply
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