Let's make a Pi Pico 2 powered video card.
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A lot has changed in the last 5 years since the Gremlin was specc'd out.
This is a Tang Nano 9k. It's about $22 on AliExpress.
It has 8640 LUTs, onboard SPI flash, and an HDMI port (!)
It could be socketed so you could take it out and use it for something else if you got bored with your ISA GlyphBlaster.
There's even a Tang Nano 20K now that has 8MB (yes MB) of SRAM on-board, and an SD-card reader. It's $45.
That's like your whole ass GlyphBlaster right there, just add bus buffers and a de-9 port.
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I'm starting to think a pico is not the appropriate thing to build a video card with.
all my fun ideas always end up with me concluding i should use an FPGA.
FPGAs are like the crabs of electronics projects. everything wants to turn into an FPGA if you give it enough time.
@gloriouscow to be honest going FPGA would kill most of the tingle that project caused in my brain.
I'm obsessed now with the idea of an IBM compatible build only out of picos.
I will follow your progress with interest anyway. I like your way to think and your presentation style. Jeep up the food work.
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@gloriouscow to be honest going FPGA would kill most of the tingle that project caused in my brain.
I'm obsessed now with the idea of an IBM compatible build only out of picos.
I will follow your progress with interest anyway. I like your way to think and your presentation style. Jeep up the food work.
@Hackbroetchen No, I get where you're coming from. I did joke that using an FPGA makes it feel like it's no longer a hack.
I start a lot of projects - its a bad habit of mine. It often seems like I abandon things, but there's a method to my madness. Many of my "new" projects are investments in acquiring knowledge and skills to finish older projects, while still getting to do fun stuff.
I've wanted to know how to program FPGAs for a while - I need the power of an FPGA to make a version of my ArduinoX86 that can run chips at full speed.
Making a digital logic simulation of the CGA would have otherwise been a distraction project, but making the Verilog MC6845 for it was the first step in learning FPGA programming. I wouldn't be sitting here with working video if I didn't already have a Verilog MC6845 written that I could just plop in.
This has all been planned. These are all pieces of a puzzle - my ultimate goal is an art piece - a cycle-accurate IBM 5150 replicated in on an FPGA, with a real 8088 at its heart, using one of those beautiful white ceramic and gold packages. I want to mount the CPU socket in a cutout in something like polished black plexiglass. So you just see the CPU, as if it were running all on its own.
It will be my love letter and tribute to the chip that started my journey into computing.
...All that said, I think I will still finalize the original, font-ROM based GlyphBlaster PCB. It's inexpensive, easy to install, and it's funny.
Maybe I'll call the FPGA version the GlyphBlaster Pro.
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@Hackbroetchen No, I get where you're coming from. I did joke that using an FPGA makes it feel like it's no longer a hack.
I start a lot of projects - its a bad habit of mine. It often seems like I abandon things, but there's a method to my madness. Many of my "new" projects are investments in acquiring knowledge and skills to finish older projects, while still getting to do fun stuff.
I've wanted to know how to program FPGAs for a while - I need the power of an FPGA to make a version of my ArduinoX86 that can run chips at full speed.
Making a digital logic simulation of the CGA would have otherwise been a distraction project, but making the Verilog MC6845 for it was the first step in learning FPGA programming. I wouldn't be sitting here with working video if I didn't already have a Verilog MC6845 written that I could just plop in.
This has all been planned. These are all pieces of a puzzle - my ultimate goal is an art piece - a cycle-accurate IBM 5150 replicated in on an FPGA, with a real 8088 at its heart, using one of those beautiful white ceramic and gold packages. I want to mount the CPU socket in a cutout in something like polished black plexiglass. So you just see the CPU, as if it were running all on its own.
It will be my love letter and tribute to the chip that started my journey into computing.
...All that said, I think I will still finalize the original, font-ROM based GlyphBlaster PCB. It's inexpensive, easy to install, and it's funny.
Maybe I'll call the FPGA version the GlyphBlaster Pro.
@gloriouscow looking forward to that!
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@gloriouscow looking forward to that!
@Hackbroetchen I might revisit the PIco stuff.
... honestly I bet a lot of the issues I was having with the Pico was just that damn capacitor.
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There's even a Tang Nano 20K now that has 8MB (yes MB) of SRAM on-board, and an SD-card reader. It's $45.
That's like your whole ass GlyphBlaster right there, just add bus buffers and a de-9 port.
Turns out the 244 buffer I pulled out of my cheapo amazon special Box o' Components was just bad, or maybe I inadvertently killed it.
In any case, I replaced it with one from the Chameleon and most of my signal issues cleared right up.
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Turns out the 244 buffer I pulled out of my cheapo amazon special Box o' Components was just bad, or maybe I inadvertently killed it.
In any case, I replaced it with one from the Chameleon and most of my signal issues cleared right up.
Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.
I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.
What does that all mean? We have smiley faces!
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Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.
I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.
What does that all mean? We have smiley faces!
Now I get to translate this hot mess into Verilog.
Yay.
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Now I get to translate this hot mess into Verilog.
Yay.
the nice thing is i can just export things to GPIO pins, and then just look at the signal in the simulation and on my scope, and just visually check that they're doing the same thing
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Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.
I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.
What does that all mean? We have smiley faces!
@gloriouscow I realized I only understand about 1/8 of all the things you say here. But I'm 100% here for this content.
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@gloriouscow I realized I only understand about 1/8 of all the things you say here. But I'm 100% here for this content.
@970uts1d3 that's fine, I understand less than 1/8 of what i post
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@970uts1d3 that's fine, I understand less than 1/8 of what i post
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@970uts1d3 that's fine, I understand less than 1/8 of what i post
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the nice thing is i can just export things to GPIO pins, and then just look at the signal in the simulation and on my scope, and just visually check that they're doing the same thing
Good enough, ship it
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Good enough, ship it
I made it worse
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I made it worse
@gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.
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I made it worse
The final version should probably not do this
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@gloriouscow Xilinx's old ISE tool had a 'schematic' mode where you could draw schematics and it would poop out HDL for that.
@ChuckMcManis digital can export your simulation to Verilog but it's quite ugly. I'm wanting to make something you can actually read that isn't just thirty chips tied together
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I made it worse
@gloriouscow sometimes my headspace looks like this
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@gloriouscow sometimes my headspace looks like this
@lucybarky col-arf-ul?
