Let's make a Pi Pico 2 powered video card.
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Right. This isn't completely baffling or anything
@gloriouscow you won minesweeper!
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Okay, if I did all this right, i should have a 14.31818MHz clock on GPIO pin 1.
Let's find out! To the workbench!
Hot damn!
looks just like the Pico clock - maybe it is my probe, lol.
So, the cool thing about FPGAs, is that this clock signal now just ... lives inside the vast and mysterious gate goo within the chip. We connected it to GPIO1, but we can connect it to just about anything, internally or externally, and we can trigger other logic on it.
It's like real legit design shit. It makes the Pico's PIO mode feel like a bit of a toy.
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Hot damn!
looks just like the Pico clock - maybe it is my probe, lol.
So, the cool thing about FPGAs, is that this clock signal now just ... lives inside the vast and mysterious gate goo within the chip. We connected it to GPIO1, but we can connect it to just about anything, internally or externally, and we can trigger other logic on it.
It's like real legit design shit. It makes the Pico's PIO mode feel like a bit of a toy.
So remember that digital logic simulation I made of the CGA card in Digital?
Digital can export your entire simulation to Verilog.
In theory, I just need to wire up the OSC pin to this 14.31818Mhz PLL clock, and wire the simulation's output pins to some GPIOs, route them out through a 244, and I'll have a picture on screen.
surely it can't be that simple?
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I'm starting to think a pico is not the appropriate thing to build a video card with.
all my fun ideas always end up with me concluding i should use an FPGA.
FPGAs are like the crabs of electronics projects. everything wants to turn into an FPGA if you give it enough time.
@gloriouscow They also walk sideways really fast!
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So remember that digital logic simulation I made of the CGA card in Digital?
Digital can export your entire simulation to Verilog.
In theory, I just need to wire up the OSC pin to this 14.31818Mhz PLL clock, and wire the simulation's output pins to some GPIOs, route them out through a 244, and I'll have a picture on screen.
surely it can't be that simple?
that would be a neat party trick but i wouldn't really learn anything and i'm sure the resulting Verilog would be spaghetti.
let's actually build this thing intentionally. Generating a clock was fun but i'm actually going to let the Pico continue to do that, and we'll treat a GPIO on the FPGA as the OSC input pin.
We'll divide it by 8, feed it to my Verilog MC6845 pre-configured for 80-column text mode, and wire up the HSYNC and VSYNC outputs to two more GPIOs.
We should get a 15.7kHz HSYNC and a 59.9kHz VSYNC out of that.
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that would be a neat party trick but i wouldn't really learn anything and i'm sure the resulting Verilog would be spaghetti.
let's actually build this thing intentionally. Generating a clock was fun but i'm actually going to let the Pico continue to do that, and we'll treat a GPIO on the FPGA as the OSC input pin.
We'll divide it by 8, feed it to my Verilog MC6845 pre-configured for 80-column text mode, and wire up the HSYNC and VSYNC outputs to two more GPIOs.
We should get a 15.7kHz HSYNC and a 59.9kHz VSYNC out of that.
This is incredibly cool.
This is a spot-on, 15.7kHz horizontal sync pulse generated the Cyclone V FPGA running my (very simplified) Motorola 6845 Verilog implementation!
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This is incredibly cool.
This is a spot-on, 15.7kHz horizontal sync pulse generated the Cyclone V FPGA running my (very simplified) Motorola 6845 Verilog implementation!
The DE-10 Nano has four user switches. The CGA outputs 4 bit color. Very convenient. Since I don't have any video memory yet, I'm just going to assign each switch to a color component, and AND it with display enable from the 6845. This should give us a well defined display rectangle on screen.
That looks something like this
wire display_en = crtc_de;
assign CGA_R = display_en ? SW[0] : 1'b0;
assign CGA_G = display_en ? SW[1] : 1'b0;
assign CGA_B = display_en ? SW[2] : 1'b0;
assign CGA_I = display_en ? SW[3] : 1'b0; -
The DE-10 Nano has four user switches. The CGA outputs 4 bit color. Very convenient. Since I don't have any video memory yet, I'm just going to assign each switch to a color component, and AND it with display enable from the 6845. This should give us a well defined display rectangle on screen.
That looks something like this
wire display_en = crtc_de;
assign CGA_R = display_en ? SW[0] : 1'b0;
assign CGA_G = display_en ? SW[1] : 1'b0;
assign CGA_B = display_en ? SW[2] : 1'b0;
assign CGA_I = display_en ? SW[3] : 1'b0;Well, it took me a bit to figure out that the 47pF capacitors right at the D-SUB connector are not optional, specifically on HSYNC. This explains why the RGB2HDMI would sync to things the real monitor wouldn't.
But hey look, FPGA CGA video!
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Well, it took me a bit to figure out that the 47pF capacitors right at the D-SUB connector are not optional, specifically on HSYNC. This explains why the RGB2HDMI would sync to things the real monitor wouldn't.
But hey look, FPGA CGA video!
I didn't properly reset the green switch which is why we got cyan instead of blue. lol. But they do all work.
The FPGA is being fed the 14.31818 clock from the Pico to simulate the ISA bus' OSC pin as an input to some future card. I'm going simulate the ISA bus with Picos until I have some idea how I'm going to connect all this business to an actual PC's ISA bus.
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I didn't properly reset the green switch which is why we got cyan instead of blue. lol. But they do all work.
The FPGA is being fed the 14.31818 clock from the Pico to simulate the ISA bus' OSC pin as an input to some future card. I'm going simulate the ISA bus with Picos until I have some idea how I'm going to connect all this business to an actual PC's ISA bus.
It's a bit silly to talk about building an FPGA-based CGA card without mentioning the Graphics Gremlin, by @tubetime
GitHub - schlae/graphics-gremlin: Open source retro ISA video card
Open source retro ISA video card. Contribute to schlae/graphics-gremlin development by creating an account on GitHub.
GitHub (github.com)
He's already made such a thing.
I'm interested in writing my own Verilog implementation, and of course I want to stick a Pico 2 W on it so we can stream video to it, but it seems sensible to fork the Gremlin instead of re-inventing the entire wheel.
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It's a bit silly to talk about building an FPGA-based CGA card without mentioning the Graphics Gremlin, by @tubetime
GitHub - schlae/graphics-gremlin: Open source retro ISA video card
Open source retro ISA video card. Contribute to schlae/graphics-gremlin development by creating an account on GitHub.
GitHub (github.com)
He's already made such a thing.
I'm interested in writing my own Verilog implementation, and of course I want to stick a Pico 2 W on it so we can stream video to it, but it seems sensible to fork the Gremlin instead of re-inventing the entire wheel.
There are some downsides, apparently this is a somewhat expensive card to build, just looking through forum discussions. But it's been five years, maybe there are better/cheaper FPGA options available today?
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There are some downsides, apparently this is a somewhat expensive card to build, just looking through forum discussions. But it's been five years, maybe there are better/cheaper FPGA options available today?
The Gremlin uses a Lattice iCE40 HX FPGA that costs about $20. That's not outrageous.
It has 7680 LUTs.
The Cyclone V I'm using has 110,000, but then again this FPGA is massive overkill. It can emulate a Nintendo 64, after all. -
The Gremlin uses a Lattice iCE40 HX FPGA that costs about $20. That's not outrageous.
It has 7680 LUTs.
The Cyclone V I'm using has 110,000, but then again this FPGA is massive overkill. It can emulate a Nintendo 64, after all.A lot has changed in the last 5 years since the Gremlin was specc'd out.
This is a Tang Nano 9k. It's about $22 on AliExpress.
It has 8640 LUTs, onboard SPI flash, and an HDMI port (!)
It could be socketed so you could take it out and use it for something else if you got bored with your ISA GlyphBlaster.
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A lot has changed in the last 5 years since the Gremlin was specc'd out.
This is a Tang Nano 9k. It's about $22 on AliExpress.
It has 8640 LUTs, onboard SPI flash, and an HDMI port (!)
It could be socketed so you could take it out and use it for something else if you got bored with your ISA GlyphBlaster.
There's even a Tang Nano 20K now that has 8MB (yes MB) of SRAM on-board, and an SD-card reader. It's $45.
That's like your whole ass GlyphBlaster right there, just add bus buffers and a de-9 port.
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I'm starting to think a pico is not the appropriate thing to build a video card with.
all my fun ideas always end up with me concluding i should use an FPGA.
FPGAs are like the crabs of electronics projects. everything wants to turn into an FPGA if you give it enough time.
@gloriouscow to be honest going FPGA would kill most of the tingle that project caused in my brain.
I'm obsessed now with the idea of an IBM compatible build only out of picos.
I will follow your progress with interest anyway. I like your way to think and your presentation style. Jeep up the food work.
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@gloriouscow to be honest going FPGA would kill most of the tingle that project caused in my brain.
I'm obsessed now with the idea of an IBM compatible build only out of picos.
I will follow your progress with interest anyway. I like your way to think and your presentation style. Jeep up the food work.
@Hackbroetchen No, I get where you're coming from. I did joke that using an FPGA makes it feel like it's no longer a hack.
I start a lot of projects - its a bad habit of mine. It often seems like I abandon things, but there's a method to my madness. Many of my "new" projects are investments in acquiring knowledge and skills to finish older projects, while still getting to do fun stuff.
I've wanted to know how to program FPGAs for a while - I need the power of an FPGA to make a version of my ArduinoX86 that can run chips at full speed.
Making a digital logic simulation of the CGA would have otherwise been a distraction project, but making the Verilog MC6845 for it was the first step in learning FPGA programming. I wouldn't be sitting here with working video if I didn't already have a Verilog MC6845 written that I could just plop in.
This has all been planned. These are all pieces of a puzzle - my ultimate goal is an art piece - a cycle-accurate IBM 5150 replicated in on an FPGA, with a real 8088 at its heart, using one of those beautiful white ceramic and gold packages. I want to mount the CPU socket in a cutout in something like polished black plexiglass. So you just see the CPU, as if it were running all on its own.
It will be my love letter and tribute to the chip that started my journey into computing.
...All that said, I think I will still finalize the original, font-ROM based GlyphBlaster PCB. It's inexpensive, easy to install, and it's funny.
Maybe I'll call the FPGA version the GlyphBlaster Pro.
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@Hackbroetchen No, I get where you're coming from. I did joke that using an FPGA makes it feel like it's no longer a hack.
I start a lot of projects - its a bad habit of mine. It often seems like I abandon things, but there's a method to my madness. Many of my "new" projects are investments in acquiring knowledge and skills to finish older projects, while still getting to do fun stuff.
I've wanted to know how to program FPGAs for a while - I need the power of an FPGA to make a version of my ArduinoX86 that can run chips at full speed.
Making a digital logic simulation of the CGA would have otherwise been a distraction project, but making the Verilog MC6845 for it was the first step in learning FPGA programming. I wouldn't be sitting here with working video if I didn't already have a Verilog MC6845 written that I could just plop in.
This has all been planned. These are all pieces of a puzzle - my ultimate goal is an art piece - a cycle-accurate IBM 5150 replicated in on an FPGA, with a real 8088 at its heart, using one of those beautiful white ceramic and gold packages. I want to mount the CPU socket in a cutout in something like polished black plexiglass. So you just see the CPU, as if it were running all on its own.
It will be my love letter and tribute to the chip that started my journey into computing.
...All that said, I think I will still finalize the original, font-ROM based GlyphBlaster PCB. It's inexpensive, easy to install, and it's funny.
Maybe I'll call the FPGA version the GlyphBlaster Pro.
@gloriouscow looking forward to that!
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@gloriouscow looking forward to that!
@Hackbroetchen I might revisit the PIco stuff.
... honestly I bet a lot of the issues I was having with the Pico was just that damn capacitor.
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There's even a Tang Nano 20K now that has 8MB (yes MB) of SRAM on-board, and an SD-card reader. It's $45.
That's like your whole ass GlyphBlaster right there, just add bus buffers and a de-9 port.
Turns out the 244 buffer I pulled out of my cheapo amazon special Box o' Components was just bad, or maybe I inadvertently killed it.
In any case, I replaced it with one from the Chameleon and most of my signal issues cleared right up.
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Turns out the 244 buffer I pulled out of my cheapo amazon special Box o' Components was just bad, or maybe I inadvertently killed it.
In any case, I replaced it with one from the Chameleon and most of my signal issues cleared right up.
Translating my digital simulation into Verilog proceeds slowly. It's nice that I can copy and paste parts of the sim and export them to Verilog in isolation, then it's a a matter of simplifying things and making connections back to the main file.
I've got the font ROM in place and the chargen serializer. To test it, I hardcoded the font ROM's upper 8 address, then I AND the serializer output directly with the color switches.
What does that all mean? We have smiley faces!
