heyyyyyy.

[dysfun@social.treehouse.systems]

@whitequark fuck yeah american megatrends

[whitequark@social.treehouse.systems]

why do they call it PCIe Stop & Scream when you enabled DS packet on DMI in with the EP bit set of out in their UT bit set

[jn@boopsnoot.de]

@whitequark i was going to ask "how" regarding the splitting, but the AliExpress search results for "pcie riser x4x4x4x4" speak for themselves

[whitequark@social.treehouse.systems]

@jn hell yeah baybee

[kc@mastodon.dragoncave.dev]

@whitequark this motherboard is a piece of modern art

[xyhhx@social.treehouse.systems]

@whitequark w-what

[xyhhx@social.treehouse.systems]

@whitequark dumb auto, obviously

[xyhhx@social.treehouse.systems]

@whitequark (i have no idea)

[hennichodernich@radiosocial.de]

@whitequark Isn't that this song by OneRepublic?

[whyrlpool@slime.global]

@artemist @whitequark need to try this along with gps disciplining the CPU clock like i did on a pi

[whitequark@social.treehouse.systems]

@xyhhx context https://social.treehouse.systems/@whitequark/116143444311471353

[xyhhx@social.treehouse.systems]

@whitequark yeah i found this after and tbh it doesn't clear much up lol

[ingalovinde@embracing.space]

@niconiconi @whitequark but that's Broadwell, just one generation before Skylake, surely its IPC is not _that_ low?
And the one they're giving out isn't even low-end, but 10-core.

[jripley@mastodon.social]

@whitequark The explanation in a random Intel chipset doc I found isn't that much better:

https://www.intel.com/content/dam/doc/datasheet/x58-express-chipset-datasheet.pdf
--
PCIe/DMI “Stop and Scream”
...per PCIe port
...disallow sending of poisoned data onto PCIe and instead convert disable the PCIe port that was the target of poisoned data
...there have been PCIe/DMI devices that have ignored the poison bit, and committed the data which can corrupt the I/O device
--

So, disable PCIe port on error, instead of tagging data as poisoned. Nice name.

[whitequark@social.treehouse.systems]

@jripley oh this makes sense!

[jripley@mastodon.social]

@whitequark I have yet to see an example of integrating PCIe, with data poisoning or not, where every edge case of error propagation can be safely accounted for. Presenting high-speed data buses directly to a CPU as addressable memory was a mistake (but we keep using PCIe nevertheless).

[mxsparks@social.treehouse.systems]

@jripley @whitequark ohhh I bet RC stands for Root Complex

[whitequark@social.treehouse.systems]

@mxsparks @jripley maaaaybe? it configures a lot more than just the PCIe Root Complex though

[ingalovinde@embracing.space]

@niconiconi @whitequark meanwhile me with C3958 I paid $700 for (including the motherboard)

Although I guess it might be a bit faster than E5-2630 v4 in multi-threading scenarios, and its TDP is also much lower...

[ingalovinde@embracing.space]

@niconiconi @whitequark But also, where do you have so many xeons from? It's not like Intel produced billions of them?