Let's make a Pi Pico 2 powered video card.
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okay this isn't that confusing
for example, these are the snake pins. you can choose from left snakes or right snakes
you know, there's a very good reason NOT to use an FPGA
when you actually use the proper tools for a job, it stops becoming a hack.
you're no longer a hacker, you're some kind of engineer or something. ugh.
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you know, there's a very good reason NOT to use an FPGA
when you actually use the proper tools for a job, it stops becoming a hack.
you're no longer a hacker, you're some kind of engineer or something. ugh.
Well, I did an FPGA thing. Can check that off the bucket list.
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okay this isn't that confusing
for example, these are the snake pins. you can choose from left snakes or right snakes
@gloriouscow this pin only does rising edges
That pin only does falling edges
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Well, I did an FPGA thing. Can check that off the bucket list.
“That's why they call me the Count!” —you, probably
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“That's why they call me the Count!” —you, probably
@argv_minus_one nobody has ever called me the count, and i hope they do not start
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Well, I did an FPGA thing. Can check that off the bucket list.
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Well, I did an FPGA thing. Can check that off the bucket list.
Okay, lets see if I can get a 14.31818MHz clock out of this thing.
We have a 50MHz clock source, on a pin called FPGA_CLK1_50.
How do we get 14.31818MHz out of that?
By attaching a PLL to it, hopefully.
module de10_clock_test (
input wire FPGA_CLK1_50,
output wire GPIO_1_0
);
wire clk_osc;
wire pll_locked;
cga_pll pll_inst (
.refclk (FPGA_CLK1_50),
.rst (1'b0),
.outclk_0 (clk_osc),
.locked (pll_locked)
);
assign GPIO_1_0 = clk_osc;
endmodule -
Okay, lets see if I can get a 14.31818MHz clock out of this thing.
We have a 50MHz clock source, on a pin called FPGA_CLK1_50.
How do we get 14.31818MHz out of that?
By attaching a PLL to it, hopefully.
module de10_clock_test (
input wire FPGA_CLK1_50,
output wire GPIO_1_0
);
wire clk_osc;
wire pll_locked;
cga_pll pll_inst (
.refclk (FPGA_CLK1_50),
.rst (1'b0),
.outclk_0 (clk_osc),
.locked (pll_locked)
);
assign GPIO_1_0 = clk_osc;
endmodulepll_instis a PLL instantiation. But notice it says nothing about like dividers or anything. We have to go into something confusingly called the IP (Incendiary Pickle) Catalog to actually configure the PLL.This is far as a I get because doing this causes Quartus to hang.
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pll_instis a PLL instantiation. But notice it says nothing about like dividers or anything. We have to go into something confusingly called the IP (Incendiary Pickle) Catalog to actually configure the PLL.This is far as a I get because doing this causes Quartus to hang.
Oh wait I just had to wait seventeen minutes. cool.
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Oh wait I just had to wait seventeen minutes. cool.
i bet there are people reading this that know how to actually use this stuff and are having themselves a sensible chuckle at my expense
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i bet there are people reading this that know how to actually use this stuff and are having themselves a sensible chuckle at my expense
when you build the PLL you get a QIP file full of nonsense
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when you build the PLL you get a QIP file full of nonsense
Okay, if I did all this right, i should have a 14.31818MHz clock on GPIO pin 1.
Let's find out! To the workbench!
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@bytex64 just out of curiosity what's the derivation of that how how did you drive it with a pico?
@gloriouscow IIRC it’s the regular fractional divider PWM mode but it was a while ago. I do have the source for it: https://github.com/bytex64/tt-munch/tree/main/clockgen
It’s also not super exact. IIRC the closest it could get was like 25.150 or something.
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Right. This isn't completely baffling or anything
@gloriouscow you won minesweeper!
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Okay, if I did all this right, i should have a 14.31818MHz clock on GPIO pin 1.
Let's find out! To the workbench!
Hot damn!
looks just like the Pico clock - maybe it is my probe, lol.
So, the cool thing about FPGAs, is that this clock signal now just ... lives inside the vast and mysterious gate goo within the chip. We connected it to GPIO1, but we can connect it to just about anything, internally or externally, and we can trigger other logic on it.
It's like real legit design shit. It makes the Pico's PIO mode feel like a bit of a toy.
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Hot damn!
looks just like the Pico clock - maybe it is my probe, lol.
So, the cool thing about FPGAs, is that this clock signal now just ... lives inside the vast and mysterious gate goo within the chip. We connected it to GPIO1, but we can connect it to just about anything, internally or externally, and we can trigger other logic on it.
It's like real legit design shit. It makes the Pico's PIO mode feel like a bit of a toy.
So remember that digital logic simulation I made of the CGA card in Digital?
Digital can export your entire simulation to Verilog.
In theory, I just need to wire up the OSC pin to this 14.31818Mhz PLL clock, and wire the simulation's output pins to some GPIOs, route them out through a 244, and I'll have a picture on screen.
surely it can't be that simple?
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I'm starting to think a pico is not the appropriate thing to build a video card with.
all my fun ideas always end up with me concluding i should use an FPGA.
FPGAs are like the crabs of electronics projects. everything wants to turn into an FPGA if you give it enough time.
@gloriouscow They also walk sideways really fast!
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So remember that digital logic simulation I made of the CGA card in Digital?
Digital can export your entire simulation to Verilog.
In theory, I just need to wire up the OSC pin to this 14.31818Mhz PLL clock, and wire the simulation's output pins to some GPIOs, route them out through a 244, and I'll have a picture on screen.
surely it can't be that simple?
that would be a neat party trick but i wouldn't really learn anything and i'm sure the resulting Verilog would be spaghetti.
let's actually build this thing intentionally. Generating a clock was fun but i'm actually going to let the Pico continue to do that, and we'll treat a GPIO on the FPGA as the OSC input pin.
We'll divide it by 8, feed it to my Verilog MC6845 pre-configured for 80-column text mode, and wire up the HSYNC and VSYNC outputs to two more GPIOs.
We should get a 15.7kHz HSYNC and a 59.9kHz VSYNC out of that.
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that would be a neat party trick but i wouldn't really learn anything and i'm sure the resulting Verilog would be spaghetti.
let's actually build this thing intentionally. Generating a clock was fun but i'm actually going to let the Pico continue to do that, and we'll treat a GPIO on the FPGA as the OSC input pin.
We'll divide it by 8, feed it to my Verilog MC6845 pre-configured for 80-column text mode, and wire up the HSYNC and VSYNC outputs to two more GPIOs.
We should get a 15.7kHz HSYNC and a 59.9kHz VSYNC out of that.
This is incredibly cool.
This is a spot-on, 15.7kHz horizontal sync pulse generated the Cyclone V FPGA running my (very simplified) Motorola 6845 Verilog implementation!
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This is incredibly cool.
This is a spot-on, 15.7kHz horizontal sync pulse generated the Cyclone V FPGA running my (very simplified) Motorola 6845 Verilog implementation!
The DE-10 Nano has four user switches. The CGA outputs 4 bit color. Very convenient. Since I don't have any video memory yet, I'm just going to assign each switch to a color component, and AND it with display enable from the 6845. This should give us a well defined display rectangle on screen.
That looks something like this
wire display_en = crtc_de;
assign CGA_R = display_en ? SW[0] : 1'b0;
assign CGA_G = display_en ? SW[1] : 1'b0;
assign CGA_B = display_en ? SW[2] : 1'b0;
assign CGA_I = display_en ? SW[3] : 1'b0;
