Time to dust off this thread!
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The alternating blinker control also works!
Aaaand I'm in integration hell
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Aaaand I'm in integration hell
There seems to be some sort of problem once more than 4 LCD buses are plugged in. But measuring the shared signal lines, the signal levels and edges as well as the power rails look totally fine, so it's not just the driver being too weak...?
It fails in a repeatable, consistent way too, so random glitches seem very unlikely.
Even at a comically slow 5 kHz clock it still fails.
But enough for today, I really need to sleep
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There seems to be some sort of problem once more than 4 LCD buses are plugged in. But measuring the shared signal lines, the signal levels and edges as well as the power rails look totally fine, so it's not just the driver being too weak...?
It fails in a repeatable, consistent way too, so random glitches seem very unlikely.
Even at a comically slow 5 kHz clock it still fails.
But enough for today, I really need to sleep@cato without knowing the circuity; do they may interfere via ground/chassis?
Where do you measure the signals: next to the source or next to the sink?
Are the glitches also present while measuring?
How do you even measure? What propes do you use?(Don't expect an expert discussion from me – those are merely ideas where i would suspected sources of errors while not knowing anything)
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@cato without knowing the circuity; do they may interfere via ground/chassis?
Where do you measure the signals: next to the source or next to the sink?
Are the glitches also present while measuring?
How do you even measure? What propes do you use?(Don't expect an expert discussion from me – those are merely ideas where i would suspected sources of errors while not knowing anything)
@Foxotronic yeah I measured at the source because it's easier but I was pretty tired, I'll do some more measurements today. Can't say if it happens while measuring yet
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There seems to be some sort of problem once more than 4 LCD buses are plugged in. But measuring the shared signal lines, the signal levels and edges as well as the power rails look totally fine, so it's not just the driver being too weak...?
It fails in a repeatable, consistent way too, so random glitches seem very unlikely.
Even at a comically slow 5 kHz clock it still fails.
But enough for today, I really need to sleepNew insights: It must be a signal integrity issue where the LCDs can't get the data quite right. See this capture. Red is clock, blue is data input, brown is data output, green is latch (irrelevant here). I am sending the same data across the whole display so even thouth the output lags behind 10 characters (600 bits), it SHOULD be the same pattern. Every group of HIGH bits is shortened by one bit.
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New insights: It must be a signal integrity issue where the LCDs can't get the data quite right. See this capture. Red is clock, blue is data input, brown is data output, green is latch (irrelevant here). I am sending the same data across the whole display so even thouth the output lags behind 10 characters (600 bits), it SHOULD be the same pattern. Every group of HIGH bits is shortened by one bit.
(also yay, finally managed to get my PicoScope to work in Linux. One less reason to boot up the old Windows install)
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New insights: It must be a signal integrity issue where the LCDs can't get the data quite right. See this capture. Red is clock, blue is data input, brown is data output, green is latch (irrelevant here). I am sending the same data across the whole display so even thouth the output lags behind 10 characters (600 bits), it SHOULD be the same pattern. Every group of HIGH bits is shortened by one bit.
pretty sure the clock (red) shouldn't have hiccups like this
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pretty sure the clock (red) shouldn't have hiccups like this
let's play around with some series termination
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let's play around with some series termination
330R on both data and clock - data is acceptable, but clock is way too weak. It still registers though! Still showing garbage anyway. But now the data out doesn't keep losing bits
Gonna try 100R on clock and leave it at 330R for data.
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R relay@relay.infosec.exchange shared this topic
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330R on both data and clock - data is acceptable, but clock is way too weak. It still registers though! Still showing garbage anyway. But now the data out doesn't keep losing bits
Gonna try 100R on clock and leave it at 330R for data.I extended my font generator thingy to allow the reverse operation, i.e. entering bytes and showing what they would look like on the LCD. I then added a function to shift the data bit by bit, and tried it with the character I am trying to send (5), and of course - one left shift and I get exactly the garbled characters I am seeing on the display. So that is what's happening. Somehow there is a single bit shift in all of the data
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I extended my font generator thingy to allow the reverse operation, i.e. entering bytes and showing what they would look like on the LCD. I then added a function to shift the data bit by bit, and tried it with the character I am trying to send (5), and of course - one left shift and I get exactly the garbled characters I am seeing on the display. So that is what's happening. Somehow there is a single bit shift in all of the data
I did confirm with the oscilloscope that what the LCD is receiving is valid data now and that the data matches what it should be. So the bit shift must have occurred outside of the timeframe I sampled with the scope
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I did confirm with the oscilloscope that what the LCD is receiving is valid data now and that the data matches what it should be. So the bit shift must have occurred outside of the timeframe I sampled with the scope
i.
i switched the clock phase (SPI mode 1 instead of 0)
and it works
i can't
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i.
i switched the clock phase (SPI mode 1 instead of 0)
and it works
i can't
why?? I tested with Arduino's shiftOut weeks ago and it worked?? Isn't shiftOut also mode 0?
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why?? I tested with Arduino's shiftOut weeks ago and it worked?? Isn't shiftOut also mode 0?
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@cato happy eating :3
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@cato happy eating :3
@Citali thanks
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@cato good noms, why is the last word orangy?
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@cato good noms, why is the last word orangy?
@mist yeah no idea, seems like that module might have been replaced and has a slightly different tone
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@cato This is so cool!
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@cato This is so cool!
@thiccpaws thank you! :3
