CIRCLE WITH A DOT

@azonenberg
Tied an (unused) FPGA bank VCCO to ground and it really wanted go to a power on this device. 0.8mm bga two vcco pins per bank. Found an alternative workaround with no mods in real life, but I think I was showing our techs on of your blog posts at one point.

Two ldos, one got copied from the other in schematic, and the vset and ilim net labels didn't get renamed. Just needed some surface cuts to split the nets.

@whitequark interesting to think about the order of operations. How many dies do they stack before the first wire bonding pass. 4? 5? Do they trust placing a die right beside the freshly made wire bonds?