CIRCLE WITH A DOT

@tyalie @mithro @matthewvenn You should also familiarize yourself with simulating your design using simulators such as Icarus Verilog or Verilator via cocotb, for example.
The fundamental knowledge you gain from FPGA design can easily be transferred to ASIC design.

@tyalie @mithro @matthewvenn Yes, Tiny Tapeout is ideal if you want to start with ASIC design right away.

As for my personal journey, I started out using the open-source FPGA toolchain (Yosys and nextpnr) with various open-source FPGA boards, such as the excellent iCEBreaker and ULX3S.
I'd recommend learning (System)Verilog or another higher-level HDL that compiles down to it, since Verilog is usually well supported by the open-source tools.

If you would also like to tape out, registration for the second shuttle run is currently open: https://buy.wafer.space/

The chip was implemented using the wafer.space LibreLane template (https://github.com/wafer-space/gf180mcu-project-template) and uses Yosys and nextpnr for the FPGA toolchain.

You can find all projects from the first wafer.space run here (ID: G801MOLE): https://github.com/wafer-space/ws-run1

wafer.space bare dies and CoB have arrived!

These are from my open-source FABulous FPGA, which was part of the first shuttle run.
It's a small FPGA with 480x LC, 6x MAC, 12x register files and 6x SRAM. The source files are available in the repository: https://github.com/mole99/gf180mcu-fabulous-fpga

#OpenSource #ASIC #FPGA

Here are some further links:

Tapeout repository: https://github.com/FPGA-Research/heichips25-tapeout
LibreLane: https://librelane.org/
IHP Open PDK: https://github.com/IHP-GmbH/IHP-Open-PDK
FABulous: https://github.com/FPGA-Research/FABulous

I'm incredibly happy to have worked on this chip! It utilizes LibreLane 3.0 (https://librelane.org) and its latest features, such as automated analog routing through non-default rules. The complete, tapeout-ready chip can be generated with just one command.

Thanks to everyone involved and for the support by Heidelberg University, BMFTR (the German Federal Ministry of Research, Technology and Space) and Chipdesign Germany for making HeiChips possible. Thank you!

To test a user project, first upload a bitstream to the FPGA which selects the project and connects it to the I/Os and SRAM as required. The bitstream is created using Yosys and nextpnr - a complete open-source FPGA toolchain.

HeiChips includes a variety of incredible user projects, among them: two different RISC-V cores, an 8-bit CPU, waveform + tone generation, a USB CDC core, a systolic array (4x4 matrices), a cryo DAC, an experimental 10 Mbps Ethernet PHY, analog standard cells and floating-gate structures, and many more!

For more information about the chip and the user projects, check out the tapeout repository: https://github.com/FPGA-Research/heichips25-tapeout

The stats are: 14 user projects, two of which are large slots and four of which are analog/mixed-signal designs.
At the center is a reprogrammable FPGA fabric that connects all the user projects, the I/Os, and the SRAM.

And another chip submitted for tapeout - HeiChips

This one has been in the works for some time, but since the shuttle was canceled last fall, it was postponed to a later one.

It's an open-source chip featuring user projects created by participants of the HeiChips Summer School 2025 (https://heichips.github.io/). How cool is that?
The chip uses 9mm² of silicon on SG13CMOS and has been submitted to IHP's Low-Cost MPW shuttle (https://dk.ihp-microelectronics.com/OpenSourceRequest.php).

More below ️

#FPGA #ASIC #OpenSource