I really appreciate the elegance of pointer tagging.
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RE: https://mstdn.social/@hkrn/116216511686844081
I really appreciate the elegance of pointer tagging. A standard 64-bit pointer isn't actually fully utilized for addressing. On most systems, virtual addresses are only 48 bits wide, leaving the upper 16 bits theoretically free to embed extra user data
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RE: https://mstdn.social/@hkrn/116216511686844081
I really appreciate the elegance of pointer tagging. A standard 64-bit pointer isn't actually fully utilized for addressing. On most systems, virtual addresses are only 48 bits wide, leaving the upper 16 bits theoretically free to embed extra user data
BTW, using those bits to store extra user data can drastically simplify object identification.
I often use it when dealing with async I/O user data in epoll or io_uring.
How I typically macro this out to pack and unpack event bits:
```
#define EV_BIT_ALL (0xFFFFull << 48)
#define GET_EV_BIT(X) ((X) & EV_BIT_ALL)
#define CLEAR_EV_BIT(X) ((X) & ~EV_BIT_ALL)
#define SET_EV_BIT(X, EV) ((X) | ((uint64_t)(EV) << 48))
``` -
BTW, using those bits to store extra user data can drastically simplify object identification.
I often use it when dealing with async I/O user data in epoll or io_uring.
How I typically macro this out to pack and unpack event bits:
```
#define EV_BIT_ALL (0xFFFFull << 48)
#define GET_EV_BIT(X) ((X) & EV_BIT_ALL)
#define CLEAR_EV_BIT(X) ((X) & ~EV_BIT_ALL)
#define SET_EV_BIT(X, EV) ((X) | ((uint64_t)(EV) << 48))
```I doubt that it will be forward compatible, though.
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I doubt that it will be forward compatible, though.
Yeah, since Ice Lake (2019), Intel supports 5-level paging, it extends the virtual memory from 48 bits to 57 bits.
https://en.wikipedia.org/wiki/Intel_5-level_paging
At least you can still use the remaining unused 7 bits wkwkwk
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