Why do DRAM chips come in different column widths (x4, x8, x16)?
-
Why do DRAM chips come in different column widths (x4, x8, x16)? Why didn't we decide that, say, all chips must be x8? What are the use cases for different bit widths?
And why do we sometimes use x4 chips in PC/server DIMMs, when we have to array twice as many chips to reach a 64-bit word size compared to x8 chips? That seems counterintuitive, it means having twice as many chips on the DIMM and makes routing more complicated.
Does anyone know?
-
Why do DRAM chips come in different column widths (x4, x8, x16)? Why didn't we decide that, say, all chips must be x8? What are the use cases for different bit widths?
And why do we sometimes use x4 chips in PC/server DIMMs, when we have to array twice as many chips to reach a 64-bit word size compared to x8 chips? That seems counterintuitive, it means having twice as many chips on the DIMM and makes routing more complicated.
Does anyone know?
@nspace Into the weeds of how SDRAM works, but I think the smaller widths are the same exact same sets of cells, just wired into columns/rows/banks differently. Lower column widths have more banks (because the lower bit width means more columns total, but the number of columns per row and rows per bank remains the same, so there's more overall banks).
More banks per chip is actually somewhat desirable because different banks can have accesses interleaved between each other, but you can only access one row of a given bank at once. So a clever SDRAM controller could access twice the number of addresses at once with an x4 chip as an x8 chip, and twice the number of addresses at once with an x8 chip than an x16 chip. ("at once" meaning not incurring the delays required to close one row and open another)
But of course it comes with the cost of needing twice the number of chips to fulfill the necessary data bus width with one access
(n.b. this is with my shaky knowledge of how SDRAM works, I'm not an expert lol)
-
Why do DRAM chips come in different column widths (x4, x8, x16)? Why didn't we decide that, say, all chips must be x8? What are the use cases for different bit widths?
And why do we sometimes use x4 chips in PC/server DIMMs, when we have to array twice as many chips to reach a 64-bit word size compared to x8 chips? That seems counterintuitive, it means having twice as many chips on the DIMM and makes routing more complicated.
Does anyone know?
@nspace some systems don't need to have a 36- or 72-bit-wide memory, so the common memory chip widths don't have a factor of 9 built in.
(the extra bits above a power of 2 are used for error correcting codes to recover from memory bit flips).
also, there tends to be a number of bits you can fit on a chip inexpensively today, and you can use that as x16 if you don't need many words of memory (and thus less stuff on your board) or x4 if you do (and fewer chips on each data line).all of the above comes from being vaguely near embedded hw design that uses ddr, but it's not actually my job.
-
@nspace Into the weeds of how SDRAM works, but I think the smaller widths are the same exact same sets of cells, just wired into columns/rows/banks differently. Lower column widths have more banks (because the lower bit width means more columns total, but the number of columns per row and rows per bank remains the same, so there's more overall banks).
More banks per chip is actually somewhat desirable because different banks can have accesses interleaved between each other, but you can only access one row of a given bank at once. So a clever SDRAM controller could access twice the number of addresses at once with an x4 chip as an x8 chip, and twice the number of addresses at once with an x8 chip than an x16 chip. ("at once" meaning not incurring the delays required to close one row and open another)
But of course it comes with the cost of needing twice the number of chips to fulfill the necessary data bus width with one access
(n.b. this is with my shaky knowledge of how SDRAM works, I'm not an expert lol)
@nytpu
Hmm I don't think this is it, x4 chips have the same number of banks as x8 chips but twice as many rows for the same overall size. Why would anyone want that?I don't think that using x4 chips gives you more banks: When DRAM chips are wired together in, say, a DIMM, the width of the data bus is fixed to something like 64 bits. By using x4 chips the designer has to wire 16 x4 chips in parallel instead of 8 x8 chips. All these chips are connected to the same address and control lines, so the same set of rows is open in all the chips at any given time.
-
@nspace some systems don't need to have a 36- or 72-bit-wide memory, so the common memory chip widths don't have a factor of 9 built in.
(the extra bits above a power of 2 are used for error correcting codes to recover from memory bit flips).
also, there tends to be a number of bits you can fit on a chip inexpensively today, and you can use that as x16 if you don't need many words of memory (and thus less stuff on your board) or x4 if you do (and fewer chips on each data line).all of the above comes from being vaguely near embedded hw design that uses ddr, but it's not actually my job.
I think that makes sense, thanks!
-
R relay@relay.infosec.exchange shared this topic
