#electronics people.

[obstsalat@mamot.fr]

@gloriouscow reset pulse at power up maybe?

[hannorein@mastodon.social]

@gloriouscow maybe something like ensuring a decisive behaviour during power up?

[jmrubillon@mastodon.ie]

@gloriouscow power on reset. The 10k combined with the input's capacitance, forms a small delay, guaranteeing a pulse at power on.

[chuckmcmanis@chaos.social]

@gloriouscow They want a glitch? I mean the parasitic capacitance of the trace will mean pin 1 changes a bit later than pin 2, so the output of the gate will be a very short pulse at power on.

[ruenahcmohr@infosec.exchange]

@gloriouscow in my early digital days, I learned that it's bad to tie a digital line straight to vcc. Today I always use resistors. I do not know what conditions not having the resistor causes damage.

[jmrubillon@mastodon.ie]

@philcowans @gloriouscow in the absence of a more complete schematic, it's fairly difficult to say what exactly it's for. Based on past high volume designs, a reset pulse is a reasonable assumption. Now, if it's connected to a crystal, I'd have to see the rest of the circuit to say what it actually does.
But a pulse at power on is what this setup generates.

[bytex64@awesome.garden]

@philcowans @gloriouscow @jmrubillon That is weird. Makes me wonder if it’s some deep voodoo magic to kickstart the oscillator or make it stabilize faster or something.

[bytex64@awesome.garden]

@RueNahcMohr @gloriouscow I think maybe some chips can be damaged if the pin voltage is higher than VCC, which might happen on startup or if the signal crosses power domains. And the resistors limit damaging currents. But that’s mostly a guess on my part.

[extelec@mstdn.social]

@gloriouscow To let the input be used by something in the future without PCB redesign ?

[bytex64@awesome.garden]

@philcowans @gloriouscow @jmrubillon Or it’s a debugging hack to allow clock injection. Pull down the input against the resistor to switch off the internal oscillator. But I’d expect a test point or something in that case.

[gloriouscow@oldbytes.space]

Sorry for the incomplete circuit.

I think what you are all saying about an initial high pulse makes sense - the F/C input to the 8284 doesn't need a pulse, but this effectively suppresses the OSC clock output for a little bit, which probably helps stability as the motherboard starts up.

[jmrubillon@mastodon.ie]

@bytex64 @philcowans @gloriouscow I've tried finding the schematics to figure it out properly, but I haven't found those yet. Maybe someone could post a link to them here and we can all be better informed?

[bytex64@awesome.garden]

@philcowans @gloriouscow @jmrubillon Gloriouscow posted high res schematics recently, which is what started this whole adventure, I think. https://archive.org/details/pcjr_schematics_4800dpi.7z

[bytex64@awesome.garden]

@gloriouscow @RueNahcMohr Well, now that I think about it that makes no sense. If it’s all tied to VCC it can’t be higher that VCC. ᖍ(ᐙ)ᖌ

[jmrubillon@mastodon.ie]

@bytex64 @philcowans @gloriouscow right, doing this on my phone, so rather suboptimal conditions. I might have to wait until my morning for a full analysis, but the XOR output being indirectly involved in the 14MHz clock output, among other things, points me to some clock generator optimisation at startup. Possibly allowing the crystal to "wake up" faster as @bytex64 hinted at.
Lemme sleep on that

[ruenahcmohr@infosec.exchange]

@bytex64 @gloriouscow I do not think it makes sense but I always do it... (ok, alsmost always)