<![CDATA[Hello and welcome to #NakedDieFriday!]]>Hello and welcome to ! This time with proper capitalisation. 🙂

The die of today is named HD6483153 and is designed by Hitachi. It fell out of a SIM card. I do not know what commercial p/n this is, if it was ever assigned one. If anyone can provide any details on what smart cards were made by Hitachi, please do so! In the meantime, we shall explore a bit. 🧵

Full-res map: http://infosecdj.net/map/hitachi/hd6483153/infosecdj_mz_nikpa40x_2/

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]]>https://board.circlewithadot.net/topic/33da85b6-c794-423d-94aa-54d9aaacb6cd/hello-and-welcome-to-nakeddiefridayRSS for NodeMon, 25 May 2026 21:29:43 GMTFri, 22 May 2026 15:22:00 GMT60<![CDATA[Reply to Hello and welcome to #NakedDieFriday! on Fri, 22 May 2026 15:52:00 GMT]]>Unlike all the others, the clock input undergoes more conditioning. After ESD protection, it is filtered and further processed to produce four signals. These are then routed into more circuitry but it is hard to immediately say whether there is more filtering or they just use the received clock for something else.

The input filter seems to be a RC one with mask-selectable options for resistance and capacitance.

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]]>https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116619026106062530https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116619026106062530Fri, 22 May 2026 15:52:00 GMT<![CDATA[Reply to Hello and welcome to #NakedDieFriday! on Fri, 22 May 2026 15:42:55 GMT]]>Apart from the usual set of 5 pads (VDD, VSS, RST, CLK, I/O), we have four more pads probed but not bonded. One is bidirectional, two are unidirectional and likely inputs, and one seems to be purely analog. The I/O pad has exactly the same structure as the bidirectional one.

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]]>https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618990413271963https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618990413271963Fri, 22 May 2026 15:42:55 GMT<![CDATA[Reply to Hello and welcome to #NakedDieFriday! on Fri, 22 May 2026 15:36:22 GMT]]>The design has everything one might expect a smartcard to have:

- A ROM unit in the upper part,
- A sea-of-gates implementing most of the logic right below it,
- An EEPROM taking more than 1/4 of the area,
- Some SRAM in the lower left.

A unit marked with a question mark is of particular interest, as it has a very regular structure. This could be the CPU data path.

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]]>https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618964638339493https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618964638339493Fri, 22 May 2026 15:36:22 GMT<![CDATA[Reply to Hello and welcome to #NakedDieFriday! on Fri, 22 May 2026 15:28:17 GMT]]>And right above it we have Pharmageddon!

- YouTube

Auf YouTube findest du die angesagtesten Videos und Tracks. Außerdem kannst du eigene Inhalte hochladen und mit Freunden oder gleich der ganzen Welt teilen.

favicon

(www.youtube.com)

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]]>https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618932885378729https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618932885378729Fri, 22 May 2026 15:28:17 GMT<![CDATA[Reply to Hello and welcome to #NakedDieFriday! on Fri, 22 May 2026 15:26:57 GMT]]>The die is fabbed using a 2-metal-layer CMOS process. The tightest routing on metal 1 seems to have 2u pitch. This can also be confirmed using these circuitry pieces. More or less.

Mask set IDs of some sort are there as well as alignment markings. Horizontal and vertical markings are separate.

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]]>https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618927647328011https://board.circlewithadot.net/post/https://infosec.exchange/users/infosecdj/statuses/116618927647328011Fri, 22 May 2026 15:26:57 GMT