<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[Topics tagged with latency]]></title><description><![CDATA[A list of topics that have been tagged with latency]]></description><link>https://board.circlewithadot.net/tags/latency</link><generator>RSS for Node</generator><lastBuildDate>Fri, 17 Apr 2026 11:35:53 GMT</lastBuildDate><atom:link href="https://board.circlewithadot.net/tags/latency.rss" rel="self" type="application/rss+xml"/><pubDate>Invalid Date</pubDate><ttl>60</ttl><item><title><![CDATA[&quot;Modern DRAM is based on a brilliant design from IBM.]]></title><description><![CDATA["Modern DRAM is based on a brilliant design from IBM.But, we're still paying for a latency penalty that's existed since the 60s!In this video, I'm introducing my personal research project (Tailslayer) that immensely reduces p99.99 latency on traditional RAM!By implementing a hedged read strategy taking advantage of (undocumented!) channel scrambling offsets, I've gotten as much as 15x reductions in tail latency.The technique works across Intel, AMD, Graviton, DDR4, DDR5, x86, ARM, you name it.Check out the C++ lib I wrote, watch the video, and try it yourself!"By @lauriewired who is frankly amazing https://youtu.be/KKbgulTp3FE#DRAM #Latency #TailSlayer]]></description><link>https://board.circlewithadot.net/topic/c15bb86e-20e2-4f95-bec8-e314bf653db6/modern-dram-is-based-on-a-brilliant-design-from-ibm.</link><guid isPermaLink="true">https://board.circlewithadot.net/topic/c15bb86e-20e2-4f95-bec8-e314bf653db6/modern-dram-is-based-on-a-brilliant-design-from-ibm.</guid><dc:creator><![CDATA[simonzerafa@infosec.exchange]]></dc:creator><pubDate>Invalid Date</pubDate></item></channel></rss>